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LTC1759 Smart Battery Charger
FEATURES
s s
DESCRIPTIO
s s
s s s s s s
s s s
Single Chip Smart Battery Charger Controller 100% Compliant (Rev 1.0) SMBus Support Allows for Operation with or without Host SMBus Accelerator Improves SMBus Timing Hardware Interrupt and SMBAlert Response Eliminate Interrupt Polling High Efficiency Synchronous Buck Charger 0.5V Dropout Voltage; Maximum Duty Cycle > 99.5% AC Adapter Current Limit Maximizes Charge Rate* 1% Voltage Accuracy; 5% Current Accuracy Up to 8A Charging Current Capability Dual 10-Bit DACs for Charger Voltage and Current Programming User-Selectable Overvoltage and Overcurrent Limits High Noise Immunity Thermistor Sensor Small 36-Lead Narrow (0.209") SSOP Package
The LTC(R)1759 Smart Battery Charger is a single chip charging solution that dramatically simplifies construction of an SBS compliant system. The LTC1759 implements a Level 2 charger function whereby the charger can be programmed by the battery or by the host. A thermistor on the battery being charged is monitored for temperature, connectivity and battery type information. The SMBus interface remains alive when the AC power adapter is removed and responds to all SMBus activity directed to it, including thermistor status (via the ChargerStatus command). The charger also provides an interrupt to the host whenever a status change is detected (e.g., battery removal, AC adapter connection). Charging current and voltage are restricted to chemistry specific limits for improved system safety and reliability. Limits are programmable by two external resistors. Additionally, the maximum average current from the AC adapter is programmable to avoid overloading the adapter when simultaneously supplying load current and charging current. When supplying system load current, charging current is automatically reduced to prevent adapter overload.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s
Portable Computers Portable Instruments Docking Stations
*US Patent Number 5,723,970
TYPICAL APPLICATIO
AC ADAPTER INPUT 0.1F
15.8k
1k 0.033
+
10F 35V V DD Al
0.1F 7 16 4 5 12 33k 33k 25 24 18 3.83k 17 28 27 11 6 20 19 UV VDD
LTC1759 DCIN DCDIV INFET VCC CLP CLN TGATE BOOSTC GBIAS BOOST SW BGATE SPIN SENSE BAT1 BAT2 VSET PGND
22 21 8 32 9 10 2 33 34 1 3 35 30 29 31 23 26 36 2.2F 0.1F 0.47F
499 SYSTEM POWER 1F 22F
SYNC SDB CHGEN VLIMIT ILIMIT DGND ISET PROG VC COMP1 AGND RNR THERM SDA SCL INTB
0.68F
1F 0.33F 0.68F 1.5k 1k
VDD 475k 10k 1k
14 15 13
Figure 1. 4A SMBus Smart Battery Charger
U
15H 0.025
U
U
+
22F SMART BATTERY
200 200 68 0.047F 0.015F INTB SCL SDA SMBus TO HOST
1759 F01
1
LTC1759
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW BOOST TGATE SW SYNC SDB AGND UV INFET CLP 1 2 3 4 5 6 7 8 9 36 PGND 35 BGATE 34 GBIAS 33 BOOSTC 32 VCC 31 BAT1 30 SPIN 29 SENSE 28 PROG 27 VC 26 VSET 25 VLIMIT 24 ILIMIT 23 BAT2 22 DCIN 21 DCDIV 20 RNR 19 THERM G PACKAGE 36-LEAD PLASTIC SSOP
Voltage at VCC, UV, BAT1, CLP,CLN, SPIN, SENSE with respect to AGND ....................- 0.3V to 27V Voltage at DCIN, BAT2 with Respect to DGND ....................................................- 0.3V to 27V Voltage at INTB, SDA, SCL, DCDIV with Respect to DGND ..................................................... - 0.3V to 7V BOOST, BOOSTC Voltage with Respect to VCC ........ 10V Voltage at VDD with Respect to DGND ........ - 0.3V to 7V SW Voltage with Respect to AGND .............. - 2V to VCC GBIAS, SYNC ............................................ - 0.3V to 10V VC, PROG, VSET Voltage with Respect to AGND ......................................................- 0.3V to 7V TGATE, BGATE Current Continuous .................. 200mA TGATE, BGATE Output Energy (per Cycle) ................ 2J PGND, DGND with Respect to AGND .................... 0.3V Current into Any Pin ......................................... 100mA Operating Ambient Temperature Range ...... 0C to 70C Operating Junction Temperature Range .............................. - 40C to 125C Storage Temperature ........................... - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1759CG
CLN 10 COMP1 11 CHGEN 12 INTB 13 SDA 14 SCL 15 VDD 16 ISET 17 DGND 18
TJMAX = 125C, JA = 85C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range (TJ = 0C to 100C), otherwise specifications are TA = 25C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER Supply and Reference DCIN, VCC Operating Voltage VCC Operating Current DCIN Operating Current UV Lockout Threshold UV Pin Input Current Battery Discharge Current VDD Operating Voltage VDD Operating Current VDD Undervoltage Lockout Switching Regulator Charging Voltage Accuracy (Notes 3, 5) Charging Current Accuracy (Note 3) 2.465V VBAT2 VMAX RSET Tolerance = 1%
q q
CONDITIONS
MIN 11
TYP
MAX 24
UNITS V mA A V A A V mA A V % %
VCC 24V VDCIN = 24V Voltage on UV Pin Rising 0V VUV 8V VUV 0.4V, All Connected Pins
q q q q
12 85 6.3 -1 40 3.0 1.35 80 6.7
20 150 7.25 5 80 5.5 2 150 2.9 1 5
q
Charging, VDD = 5.5V, Shorted Thermistor Not Charging, VDD = 5.5V
q
1.6 -1 -5
2.2
2
U
W
U
U
WW
W
LTC1759
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range (TJ = 0C to 100C), otherwise specifications are TA = 25C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER BOOST Pin Current CONDITIONS VBOOST = VSW + 8V, 0V VSW 20V TGATE High TGATE Low Measured at (VBOOST - VSW) Low to High Hysteresis VBOOSTC = VCC + 8V 11V VCC 24V, 0V VBAT 20V RSET = 4.93k RSET = 49.3k VSDB = High VSDB = Low (Shutdown) VSDB = High, VSPIN = 12.6V VSDB = Low 0.5mA Output Current Output Current from 50A to 500A 0.5mA Output Current 0.5mA Output Current VC = 1V, IVC = 1A Ouput Current from 50A to 500A VCC 11V, IGBIAS 15mA, VSDB = High ITGATE 20mA IBGATE 20mA ITGATE 50mA IBGATE 50mA VINFET = VCC - 6V VCC Not Connected, IINFET < - 2A VCC = 12.4V, (VCC - VINFET) 2V VSDB = Low, ITGATE = IBGATE = 10A VDCDIV Rising from 0.8V to 1.2V VDCDIV = 1V AC_PRESENT = 1, VDCIN = 6V AC_PRESENT = 1, VDCIN = 6V 0.9 VSYNC = 0V VSYNC = 2V
q q q q q q q q q q q q q
MIN
TYP 2 2
MAX 3 3 7.6
UNITS mA mA V V mA
VBOOST Threshold to Turn TGATE Off (Note 6) BOOSTC Pin Current Sense Amplifier CA1 Gain and Input Offset Voltage (With RS2 = RS3 = 200) (Measured Across RS1) (Note 4) CA1 Bias Current (SENSE, BAT1) CA1 Input Common Mode Range SPIN Input Current CL1 Turn-On Threshold CL1 Transconductance CLP Input Current CLN Input Current CA2 Transconductance VA Transconductance (Note 5) Gate Drivers VGBIAS VTGATE High (VTGAGE - VSW) VBGATE High VTGATE Low (VTGATE - VSW) VBGATE Low INFET "ON" Clamping Voltage (VCC - VINFET) INFET "ON" Drive Current INFET "OFF" Clamping Voltage INFET "OFF" Drive Current VTGATE, VBGATE at Shutdown Trip Points DCDIV Threshold DCDIV Hysteresis DCDIV Input Bias Current Power-Fail Indicator (VBAT2 VDCIN) (Note 7) Power-Fail Indicator Hysteresis (VBAT2 VDCIN) SYNC Pin Threshold SYNC Pin Input Current
6.8
7.3 0.25 1
92 7
100 10 - 50
108 13 -120 -10 VCC - 0.3 2 10
mV mV A A V mA A mV mho A mA mho mho V V V
- 0.25
87 0.5
92 1 1 0.8
97 3 3 2 300 1 9.6
150 0.21 8.4 5.6 6.2
200 0.6 9.1 6.6 7.2
0.8 0.8 6.5 8 7.8 20 1.4 -2.5 1 0.9 1.0 25 1.1 100 0.84 0.89 0.02 1.4 2.0 - 500 -30 0.97 9
V V V mA V mA V V mV nA V/V V/V V A A
q
q q
3
LTC1759
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range (TJ = 0C to 100C), otherwise specifications are TA = 25C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER Thermistor Decoder (Note 11) Combined Input Leakage on RNR and THERM Thermistor Trip (COLD/OR) Thermistor Trip (IDEAL/COLD) Thermistor Trip (HOT/IDEAL) Thermistor Trip (UR/HOT) DACs Charging Current Resolution Charging Current Granularity Guaranteed Monotonic Above IMAX/16 RILIMIT = 0 RILIMIT = 10k 1 % RILIMIT = 33k 1 % RILIMIT = Open (or Short to VDD) RILIMIT = 0 RILIMIT = 10k 1 % RILIMIT = 33k 1 % RILIMIT = Open (or Short to VDD) VISET = 2.7V Guaranteed Monotonic (2.5V VBAT 21V) RVLIMIT = 0 RVLIMIT = 10k 1 % RVLIMIT = 33k 1 % RVLIMIT = 100k 1 % RVLIMIT = Open (or Short to VDD) RVLIMIT = 0 RVLIMIT = 10k 1 % RVLIMIT = 33k 1 % RVLIMIT = 100k 1 % RVLIMIT = Open (or Short to VDD) (Note 2)
q q q q q
CONDITIONS
MIN
TYP
MAX 200
UNITS nA k k k bits
RWEAK = 475k 1% RNR = 10k 1 % RNR = 10k 1 % RUR = 1k 1 %
q q q q
80 26.4 2.64 440 10
100 30 3 500
120 33.6 3.36 560
1 2 4 8 80 1023 2046 4092 8184 25 1 10 16 16 32 32 32 8.33 12.50 16.67 20.82 8.432 12.64 16.864 21.056 32.736 8.485 12.72 16.97 21.18
mA mA mA mA mA mA mA mA mA A bits mV mV mV mV mV V V V V V V V 0.4 1 1 0.4 V A A V A V V 2 8 V A s
Wake-Up Charging Current (IWAKE-UP) (Note 8) Charging Current Limit (IMAX)
ISET RDS(ON) ISET IOFF Charging Voltage Resolution Charging Voltage Granularity
Charging Voltage Limit
Logic Levels (Note 12) SCL/SDA Input Low Voltage (VIL) SCL/SDA Input High Voltage (VIH) SDA Output Low Voltage (VOL) SCL/SDA Input Current (IIL) SCL/SDA Input Current (IIH) INTB Output Low Voltage (VOL) INTB Output Pull-Up Current CHGEN Output Low Voltage (VOL) CHGEN Output High Voltage (VOH) SDB Shutdown Threshold SDB Pin Current Power-On Reset Duration 0V VSDB 3V VDD Ramp from 0V to > 3V in < 5s 100 IPULLUP = 350A VSDA, VSCL = VIL VSDA, VSCL = VIH IPULLUP = 500A VINTB = VOL IOL = 200A IOH = - 200A
q q q q q q q q q VDD - 0.4 q
0.6 1.4
3.5
10
17.5 0.4
1
4
LTC1759
ELECTRICAL CHARACTERISTICS
The q denotes specifications which apply over the full operating temperature range (TJ = 0C to 100C), otherwise specifications are TA = 25C. VCC = DCIN = 18V, VBAT1, 2 = 12.6V, VDD = 3.3V unless otherwise specified.
PARAMETER Charger Timing VTGATE, VBGATE Rise/Fall Time TGATE, BGATE Peak Drive Current Regulator Switching Frequency Synchronization Frequency Maximum Duty Cycle in Start-Up Mode (Note 9) tTIMEOUT for Wake-Up Charging a Cold or Underrange Battery SCL Serial Clock High Period (tHIGH) SCL Serial Clock Low Period (tLOW) SDA/SCL Rise Time (t r) SDA/SCL Fall Time (t f) SMBus Accelerator Boosted Pull-Up Current Start Condition Setup Time (t SU:STA) Start Condition Hold Time (t HD:STA) SDA to SCL Rising-Edge Setup Time (t SU:DAT) SDA to SCL Falling-Edge Hold Time, Slave Clocking in Data (t HD:DAT) t TIMEOUT Between Receiving Valid ChargingCurrent() and ChargingVoltage() Commands (Note 10) Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This limit is greater than the absolute maximum for the charger. Therefore, there is no effective limitation on voltage when this option is selected. If the charger is requested to charge with a higher voltage than the nominal limit, the VOLTAGE_OR bit will be set. Note 3: Total system accuracy from SMBus request to output voltage or output current. Note 4: Test Circuit #1. Note 5: Voltage accuracy is calculated using measured reference voltage, obtained from VSET pin using Test Circuit #2, and VDAC resistor divider ratio. Note 6: When supply and battery voltage differential is low, high oscillator duty cycle is required. The LTC1759 has a unique design to achieve duty cycle greater than 99% by skipping cycles. Only when VBOOST drops below the comparator threshold, will TGATE be turned off. See Applications Information section. VDD = 3V IPULLUP = 350A, CLOAD = 150pF IPULLUP = 350A, CLOAD = 150pF CLOAD = 150pF 1nF Load 10nF Load
q q q q
CONDITIONS
MIN
TYP 25 1
MAX
UNITS ns A
170 240 85 140
200 90 175
230 280 210
kHz kHz % sec
SMBus Timing (refer to System Management Bus Specification, Revision 1.0, section 2.1 for timing diagrams) (Note 12)
q q q q q q q q q q
4 4.7 1000 30 1 4.7 4.0 250 300 140 175 210 2.5 300
s s ns ns mA s s ns ns sec
Note 7: Power failure bit is set when the battery voltage is above 89% of the power adapter voltage (VDCIN). Note 8: The charger provides wake-up current when a battery is inserted into the connector, prior to the battery requesting charging current and voltage. See Smart Battery Charger Specification (Revision 1.0), section 6.1.3 and 6.1.8. Note 9: In system start-up, C6 (boost capacitor) has no charge stored in it. The LTC1759 will keep TGATE off, and turn BGATE on for 0.2s, thus charging C6. A comparator senses VBOOST and switches to the normal PWM mode when VBOOST is above its threshold. Note 10: Refer to Smart Battery Charge Specification (Revision 1.0), section 6.1.2. Note 11: Maximum total external capacitance on RNR and THERM pins is 75pF. Note 12: SMBus operation guaranteed by design from -40C to 85C.
5
LTC1759 TYPICAL PERFOR A CE CHARACTERISTICS
Charger Efficiency
100 16.8V 95 12.6V EFFICIENCY (%) 90
LTC1759 5V VCC = 5V CLD = 200pF TA = 25C
85 80
0V RPULLUP = 15k
DCDIV (V)
75 VIN = 20V 70 0.5 1.5 2.5 3.5 CHARGING CURRENT (A)
1759 G09
Current from Battery vs Battery Voltage (Does Not Include VDD Current)
90 TA = 25C 80 70 60
IBAT (A)
OUTPUT CURRENT ERROR (mA)
50 40
IDD (A)
30 20 10 6 8 10 12 14 16 18 VBAT (V) 20 22 24 70 60 3.0
Low Current Mode
350
OUTPUT VOLTAGE ERROR (mV)
250 200 150 100 50 0 0
OUTPUT VOLTAGE ERROR (mV)
300
OUTPUT CURRENT (mA)
RILIMIT = 33k VIN = 15V VOUT = 12V TA = 25C CPROG = 1nF RSET = 3.83k
50
100 150 200 250 CHARGING CURRENT (mA)
6
UW
1759 G04 1759 G01
SMBus Accelerator Operation
1.10
DCDIV Trip Point vs Temperature
1.05 VDD = 5.5V
1.00 VDD = 3V 0.95
0.90
1s/DIV
1759 G02
0
10
20 30 40 50 60 TEMPERATURE (C)
70
80
1759 G03
IDD vs VDD (Not Charging)
120 TA = 25C 110 100 90 80 -10 -20 0
Programmed Current Accuracy
VDD = 5.5V
VDD = 3V -30 -40 -50 -60 256
RILIMIT = 33k VIN = 15V VOUT = 12V TA = 25C 1256 2256 3256 CHARGING CURRENT (mA) 4256
1759 G06
3.5
4.0 4.5 VDD (V)
5.0
5.5
1759 G05
Charging Voltage Error
0 -5 -10 -15 -20 -25 RVLIMIT = 0 LOAD CURRENT = 15mA TA = 25C VDD = 5.5V VDD = 3V 0 -5 -10 -15
Charging Voltage Error
VDD = 5.5V
VDD = 3V -20 -25 -30 2000 RVLIMIT = 33k LOAD CURRENT = 15mA TA = 25C 6000 10000 14000 CHARGING VOLTAGE (mV) 18000
1759 G08
300
-30 2000 3000 4000 5000 6000 7000 8000 9000 CHARGING VOLTAGE (mV)
1759 G07
LTC1759
PIN FUNCTIONS
Input Power-Related Pins
UV (Pin 7): Charger Section Undervoltage Lockout Pin. The rising threshold is 6.7V with a hysteresis of 0.5V. Switching stops in undervoltage lockout. Connect this input to the input voltage source with no resistor divider. UV must be pulled below 0.7V when there is no input voltage source (5k resistor from adapter output to ground is required) to obtain the lowest quiescent battery current. INFET (Pin 8): Gate Drive to Input P-channel FET. For very low dropout applications, use an external P-channel FET to connect the adapter output and VCC. INFET is clamped to 7.8V below VCC. CLP (Pin 9): Positive Input to the Input Current Limit Amplifier CL1. When used to limit supply current, a filter (R3 and C1 of Figure 10) is needed to filter out the switching noise. The threshold is set at 92mV. CLN (Pin 10): Negative Input to the Input Current Limit Amplifier CL1. It should be connected to VCC (to the VCC bypass capacitor C2 for less noise). COMP1 (Pin 11): Compensation Node for the Input Current Limit Amplifier CL1. At input adapter current limit, this node rises to 1V. By forcing COMP1 low with an external transistor, amplifier CL1 will be defeated (no adapter current limit). COMP1 can source 200A. Ground (to AGND) this pin if the adapter current limiting function is not used. SW (Pin 3): This pin is the reference point for the floating topside gate drive circuitry. It is the common connection for the top and bottom side switches and the output inductor. This pin switches between ground and VCC with very high dv/dt rates. Care needs to be taken in the PC layout to keep this node from coupling to other sensitive nodes. A 1A Schottky clamping diode should be placed very close to the chip from the ground pin to this pin to prevent the chip substrate diode from turning on. See Applications Information for more details. SYNC (Pin 4): External Clock Synchronization Input. Pulse width range: 10% to 90%. SDB (Shutdown Bar) (Pin 5): Active Low Digital Input. The charger is disabled when asserted. This pin is connected to the CHGEN pin to enable charger control through the SMBus interface. CHGEN (Pin 12): Digital Output to Enable Charger Function. Connect CHGEN to SDB. ISET (Pin 17): Open-Drain CMOS Switch to DGND. An external resistor, RSET, is connected from ISET to the current programming input, the PROG pin of the battery charger section, which sets the range of the charging current. ILIMIT (Pin 24): An external resistor is connected between this pin and DGND. The value of the external resistor programs the range and resolution of the programmed charger current. See Electrical Characteristics table for more information. VLIMIT (Pin 25): An external resistor is connected between this pin and DGND. The value of the external resistor programs the range and resolution of the VSET divider. See Electrical Characteristics table for more information. VSET (Pin 26): This is the tap point of the programmable resistor divider, which provides battery voltage feedback to the charger.
Battery Charging-Related Pins
BOOST (Pin 1): This pin is used to bootstrap and supply power for the topside power switch gate drive and control circuity. In normal operation, VBOOST is powered from an internally generated 8.6V regulator VGBIAS, VBOOST VCC + 9.1V when TGATE is high. Do not force an external voltage on BOOST pin. TGATE (Pin 2): This pin provides gate drive to the topside power FET. When TGATE is driven on, the gate voltage will be approximately equal to VSW + 6.6V. A series resistor of 5 to 10 should be used from this pin to the gate of the topside FET.
U
U
U
7
LTC1759
PIN FUNCTIONS
VC (Pin 27): This is the control signal of the inner loop of the current mode PWM. Switching starts at 0.9V. Higher VC corresponds to higher charging current in normal operation. A capacitor of at least 0.33F to AGND filters out noise and controls the rate of soft start. PROG (Pin 28): This pin is for programming the charging current and for system loop compensation. During normal operation, the pin voltage is approximately 2.465V. SENSE (Pin 29): Current Amplifier CA1 Input. Sensing must be at the positive terminal of the battery. SPIN (Pin 30): This pin is for the internal amplifier CA1 bias. It must be connected to RSENSE as shown in Figure 1. BAT1 (Pin 31): Current Amplifier CA1 Input. BOOSTC (Pin 33): This pin is used to bootstrap and supply the current sense amplifier CA1 for very low dropout conditions. VCC can be as low as only 0.4V above the battery voltage. A diode and a capacitor are needed to get the voltage from VBOOST. If low dropout is not needed and VCC is always 3V or greater than VBAT, this pin can be left floating or tied to VCC. Do not force this pin to a voltage lower than VCC. BGATE (Pin 35): Drives the gate of the bottom external N-channel FET of the charger buck converter.
Monitor/Fault Diagnostic Pins
DCDIV (Pin 21): Supply Divider Input. This is a high impedance comparator input with a 1V threshold (rising edge) and hysteresis. DCIN (Pin 22): Input connected to the DC input source to monitor the DC input for power-fail condition. BAT2 (Pin 23): Sensing Point for Voltage Control Loop. Connect this to the positive terminal of the battery.
8
U
U
U
Internal Power Supply Pins
AGND (Pin 6): DC Accurate Ground for Analog Circuitry. VDD (Pin 16): Low Voltage Power Supply Input. Bypass this pin with 0.1F. DGND (Pin 18): Ground for Digital Circuitry and DACs. Should be connected to AGND at the negative terminal of the charger output filter capacitor. VCC (Pin 32): Power Input for Battery Charger Section. Bypass this pin with 0.47F. GBIAS (Pin 34): 8.6V Regulator Output for Bootstrapping VBOOST and VBOOSTC. A bypass capacitor of at least 2F is needed. Switching will stop if VBOOST drops below 7.1V. PGND (Pin 36): High Current Ground Return for Charger Gate Drivers.
SBS Interface Pins
INTB (Interrupt Bar) (Pin 13): Active Low Interrupt Output to Host. Signals host that there has been a change of status in the charger registers and that the host should read the LTC1759 status registers to determine if any action on its part is required. This signal can be connected to the optional SMBALERT# line of the SMBus. Open drain with weak current source pull-up to VDD (with Schottky to allow it to be pulled to 5V externally, see Figure 2). SDA (Pin 14): SMBus Data Signal from Main (Hostcontrolled) SMBus. SCL (Pin 15): SMBus Clock Signal from Main (HostControlled) SMBus. External pull-up resistor is required. THERM (Pin 19): Thermistor Force/Sense Pin to Smart Battery. See Electrical Characteristics table for more detail. Maximum allowed combined capacitance on THERM and RNR is 75pF. RNR (Pin 20): Thermistor Force/Sense Pin to Smart Battery. See Electrical Characteristics table for more detail. Maximum allowed combined capacitance on THERM and RNR is 75pF.
LTC1759
BLOCK DIAGRA
UV 7 + +
BAT1 31 VCC 32 SDB 5
6.7V
6.7V 1 BOOST SHDN PWM LOGIC 8.9V 34 GBIAS 35 BGATE 36 PGND 33 BOOSTC B1 + - 1k CA1 + BAT1 28 PROG - VREF - 2 TGATE 3 SW
1.3V SYNC 4 ONE SHOT 200kHz OSC SLOPE COMP S Q R
CLP 9 CLN 10 COMP1 11
AC_PRESENT VDD 10A
PWR_FAIL INTB 13 CHARGER CONTROLLER CHGEN 12 THERM 19 RNR 20 SCL 15 SDA 14 DGND 18 THERMISTOR DECODER
SMBus CONTROLLER
13
Figure 2
-
+
-
-
+
92mV +
75k VA + 290k
CL1
-
VC 27
-
AGND 6
C1
+ CA2
-
-
0.2V + -
+
-
+
W
VCC 7.8V 8 INFET 30 SPIN 29 SENSE VREF 21 DCDIV 22 DCIN 1V 20k + 812.5k 23 BAT2 65k 612k 26 VSET 72k 10-BIT VOLTAGE DAC LIMIT DECODER 24 ILIMIT 25 VLIMIT 10-BIT CURRENT DAC 17 ISET 16 VDD
1759 F02
9
LTC1759
TEST CIRCUITS
Test Circuit 1
LTC1759 SPIN SENSE RS3 200 RS2 200 RSENSE 10
+
CA1 1k VREF
VC 0.047F 75k
CA2
+
1k LT1006
+
-
0.65V 20k
IPROG
0.47F
RSET
2.465V
10
+
+
-
- +
1F 300 RSET
PROG 2k
-
BAT1
+
VBAT
PROG
1759 TC01
Test Circuit 2
LTC1759 VSET
+
VA
-
VREF
2nF LT1013
1759 TC02
LTC1759
OPERATIO
Overview (Refer to Block Diagram and Figure 10) The LTC1759 is composed of a battery charger section, a charger controller, two 10-bit DACs to control charger parameters, a thermistor decoder, limit decoder and an SMBus controller block. If no battery is present, the thermistor decoder indicates a THERM_OR condition and charging is disabled by the charger controller (CHGEN = Low). Charging will also be disabled if AC_PRESENT is low, or the battery thermistor is decoded as THERM_HOT. If a battery is inserted or AC power is connected, the battery will be charged with an 80mA "wake-up" current. The wake-up current is discontinued after three minutes if the thermistor is decoded as THERM_UR or THERM_COLD, and the battery or host doesn't transmit charging commands. The SMBus controller block receives ChargingCurrent() and ChargingVoltage() commands via the SMBus. If ChargingCurrent() and ChargingVoltage() command pairs are received within a three-minute interval, the values are stored in the current and voltage DACs and the charger controller asserts the CHGEN line if the decoded thermistor value will allow charging to commence. ChargingCurrent () and ChargingVoltage() values are compared against limits programmed by the limit decoder block; if the commands exceed the programmed limits these limits are substituted and overrange flags are set. The charger controller will assert INTB whenever a status change is detected. The host may query the charger, via the SMBus, to obtain ChargerStatus() information. INTB will be deasserted upon a successful read of ChargerStatus() or a successful Alert Response Address (ARA) request. Battery Charger Section The LTC1759 is synchronous current mode PWM stepdown (Buck) switcher. The battery DC charging current is programmed with a current DAC via the SMBus interface. Amplifier CA1 converts the charging current through RSENSE to a much lower current IPROG (IPROG = IBAT * RSENSE /RS2) fed into the PROG pin. Amplifier CA2 compares the output of CA1 with the programmed current and drives the PWM loop to force them to be equal. High DC
U
accuracy is achieved with averaging capacitor CPROG. Note that IPROG has both AC and DC components. IPROG generates a ramp signal that is fed to the PWM control comparator C1 through buffer B1 and level shift resistors forming the current mode inner loop. The BOOST pin supplies the top power switch gate drive. The LTC1759 generates a 8.9V VGBIAS for bootstrapping VBOOST and VBOOSTC as well as to drive the bottom power FET. The BOOSTC pin supplies the current amplifier CA1 with a voltage higher than VCC for low dropout applications. Amplifier VA reduces the charging current when the battery voltage reaches the set voltage programmed by the VDAC and the 2.465V reference voltage. The amplifier CL1 monitors and limits the input current, normally from the AC adapter, to a preset level (92mV/ RCL). At input current limit, CL1 will supply the programming current IPROG and thus reduce battery charging current. The INFET pin drives an external input P-channel FET for low dropout applications. SMBus Interface All communications over the SMBus are interpreted by the SMBus controller block. The SMBus controller is an SMBus slave device. All internal LTC1759 registers may be updated and accessed through the SMBus controller, and charger controller as required. The SMBus protocol is a derivative of the I2CTM bus (Reference "I 2C-Bus and How to Use It, V1.0" by Philips and "System Management Bus Specification" by the Smart Battery System Organization*, for a complete description of the bus protocol requirements.) All data is clocked into the shift register on the rising edge of SCL. All data is clocked out of the shift register on the falling edge of SCL. Detection of an SMBus Stop condition, or power-on reset via the VDD undervoltage lockout, will reset the controller to an initial state at any time. The LTC1759 command set is interpreted by the SMBus controller and passed onto the charger controller block as control signals or updates to internal registers.
I2C is a trademark of Philips Electronics N.V. *http://www. SBS-FORUM.org
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LTC1759
OPERATIO
FUNCTION ChargerSpecInfo() ChargerMode() ChargerStatus() ChargingCurrent() ChargingVoltage() AlarmWarning() LTCVersionFunction()
Table 1: Supported Charger Functions
SMBus ADDRESS (7-BIT) b0001_001 b0001_001 b0001_001 b0001_001 b0001_001 b0001_001 b0001_001 b0001_001 b0001_001 b0001_001 b0001_100 COMMAND CODE (8-BIT hex) h11 h12 h13 h14 h15 h16 h3c h3d h3e h3f N/A ACCESS r w r w w w r - - - Read Byte DATA TYPE Register Register Register Register Register Control Register Not Supported Not Supported Not Supported Interrupt Address
OptionalMfgFunction3() OptionalMfgFunction2() OptionalMfgFunction1() Alert Response Address1
1Read-byte format. 89h is returned as the interrupt address of the LTC1759. Rev 1.0 SMBus Compliant.
Table 2: SMBus Word Bit Definitions for All Allowed LTC1759 Functions
WORD BIT MAPPING 3:0 POWER-ON RESET VALUE (BINARY) 0001
FUNCTION ChargerSpecInfo
SELECTOR_SUPPORT
ChargerMode()
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FIELD CHARGER_SPEC ALLOWED VALUES * The CHARGER_SPEC Reports the Version of the Smart Battery Charger Specification the Charger Supports * 0001 - Version 1.0 * All Other Codes Reserved * Always Returns 0001 * Read Only. Write Will NACK * 0 - Charger Does Not Support the Optional Smart Battery Selector Commands * 1 - Charger Supports the Optional Smart Battery Selector Commands * Always Returns 0 * Read Only. Write Will NACK * These Bits Are Reserved and Must Return Zero * Read Only. Write Will NACK * * * * 0 - Enable Charging (Power-On Default) 1 - Inhibit Charging Write Only. Read Will NACK Cleared to Power-On Reset Value When: 1) POR_RESET = 1 2) AC_PRESENT = 0 3) BATTERY_PRESENT = 0 4 0 Reserved INHIBIT_CHARGE 15:5 0 0 0 ENABLE_POLLING 1 0 * 0 - Disable Polling (Power-On Default for Smart Battery Controlled Chargers) * 1 - Enable Polling (Power-On Default for Host Controlled Chargers). * Ignored by LTC1759 * Write Only. Read Will NACK * * * * 0 - Mode Unchanged (Default) 1 - Set Charger to Power-On Defaults This Reset Only Affects the Charger_Controller Block Write Only. Read Will NACK POR_RESET 2 0
LTC1759
OPERATIO
FUNCTION
ChargerStatus()
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FIELD RESET_TO_ZERO WORD BIT MAPPING 3 POWER-ON RESET VALUE (BINARY) 0 ALLOWED VALUES * 0 - Charging Value Unchanged * 1 - Set Charging Values to Zero NOTE: This function is implemented by forcing the charger to CHARGING_NONE_STATE and not allowing charge to resume until a valid ChargingCurrent() and ChargingVoltage() Pair Is received. * Write Only. Read Will NACK * Not Implemented. Writes to These Bits Are Ignored. * Write Only. Read Will NACK This Is the ChargerMode() INHIBIT_CHARGE Bit * 0 - Charger Is Enabled * 1 - Charger Is Inhibited * Read Only. Write Will NACK * 0 - Charger Is in Slave Mode (Polling Disabled) * 1 - Charger Is in Master Mode (Polling Enabled) * Always Returns 0 * Read Only. Write Will NACK * * * * * * * * * * * * * * 0 - Charger's Output Voltage Is in Regulation 1 - Requested ChargingCurrent() Is Not Being Met Not Supported; Always Returns 0 Read Only. Write Will NACK 0 - Charger's Output Current Is in Regulation 1 - Requested ChargingCurrent() Is Not Being Met Not Supported; Always Returns 0 Read Only. Write Will NACK 00 - Reserved 01 - Charger Is a Smart Battery Controlled 10 - Reserved 11 - Charger Is a Host Controlled Always Returns 01 Read Only. Write Will NACK Reserved CHARGE_INHIBITED 15:4 0 0 0 MASTER_MODE 1 0 VOLTAGE_NOTREG 2 0 CURRENT_NOTREG 3 0 LEVEL_3:LEVEL_2 5:4 01 CURRENT_OR 6 0 * 0 - ChargingCurrent() Value Is Valid * 1 - ChargingCurrent() Value Is Invalid * This Value Is Valid Only When Charging with CHARGE_INHIBITED = 0 or 1 * Read Only. Write Will NACK * 0 - ChargingVoltage() Value Is Valid * 1 - ChargingVoltage() Value Is Invalid * This Value Is Valid Only When Charging with CHARGE_INHIBITED = 0 or 1 * Read Only. Write Will NACK * 0 - Thermistor Indicates Not Overrange * 1 - Thermistor Indicates Overrange * Read Only. Write Will NACK * 0 - Thermistor Indicates Not Cold * 1 - Thermistor Indicates Cold * Read Only. Write Will NACK * 0 - Thermistor Indicates Not Hot * 1 - Thermistor Indicates Hot * Read Only. Write Will NACK VOLTAGE_OR 7 0 THERM_OR 8 Value THERM_COLD 9 Value THERM_HOT 10 Value
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LTC1759
OPERATIO
FUNCTION
ChargingCurrent()
CHARGING_CURRENT [15:0]
ChargingVoltage()
CHARGING_VOLTAGE [15:0]
AlarmWarning()
TERMINATE_CHARGE_ ALARM RESERVED_ALARM1
OVER_TEMP_ALARM
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FIELD THERM_UR WORD BIT MAPPING 11 POWER-ON RESET VALUE (BINARY) Value ALLOWED VALUES * 0 - Thermistor Indicates Not Underrange * 1 - Thermistor Indicates Underrange * Read Only. Write Will NACK * 0 - Charger Not Alarm Inhibited * 1 - Charger Alarm Inhibited. This Bit Is Set but Never Cleared by AlarmWarning() * Read Only. Write Will NACK * Cleared to Power-On Reset Value When: 1) POR_RESET = 1 2) BATTERY_PRESENT = 0 3) AC_PRESENT = 0 4) A Valid ChargingVoltage(), ChargingCurrent() Pair Is Received * 0 - VBAT/VDCIN < 0.9 * 1 - VBAT/VDCIN > 0.9 * Read Only. Write Will NACK * 0 - Battery Is Not Present * 1 - Battery Is Present * Read Only. Write Will NACK * 0 - Charge Power Is Not Available * 1 - Charge Power Is Available * Read Only. Write Will NACK * Unsigned Integer Representing Charger Current in mA * Three Possible Responses - Supply the Current Requested - Supply Its Programmatic Maximum Current If the Request Is Greater Than Its Programmatic Value and Less Than hffff - Supply Its Maximum Safe Current If the Request Is hffff [Supply Current Required to Meet ChargingVoltage()]. * Write Only. Read Will NACK * Unsigned Integer Representing Charger Voltage in mV * Three Possible Responses - Supply the Voltage Requested - Supply Its Programmatic Maximum Voltage If the Request Is Greater Than Its Programmatic Value and Less Than hffff - Supply Its Maximum Voltage If the Request Is hffff [Supply Voltage Required to Meet ChargingCurrent()]. * Write Only. Read Will NACK * 1 - Terminate Charging Immediately * Write Only. Read Will NACK * Writing a 0 to This Bit Will Be Ignored * 1 - Terminate Charging Immediately * Write Only. Read Will NACK * Writing a 0 to This Bit Will Be Ignored. * 1 - Terminate Charging Immediately * Write Only. Read Will NACK * Writing a 0 to This Bit Will Be Ignored. * 1 - Terminate Charging Immediately * Write Only. Read Will NACK * Writing a 0 to This Bit Will Be Ignored. ALARM_INHIBITED 12 0 POWER_FAIL 13 Value BATTERY_PRESENT 14 Value AC_PRESENT 15 Value 15:0 0 15:0 0 OVER_CHARGED_ ALARM 15 0 14 0 13 0 12 0
LTC1759
OPERATIO
FUNCTION
LTCVersionFunction ()
SMBus Accelerator Pull-Ups Both SCL and SDA have SMBus accelerator circuits which reduce the rise time on systems with significant capacitance on the two SMBus signals. The dynamic pull-up circuitry detects a rising edge on SDA or SCL and applies 2mA to 5mA pull-up to VDD for approximately 1s (external pull-up resistors are still required to supply DC current). This action allows the bus to meet SMBus rise time
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FIELD TERMINATE_ DISCHARGE_ALARM WORD BIT MAPPING 11 POWER-ON RESET VALUE (BINARY) 0 ALLOWED VALUES * This Bit May Be Used to Signal That the Charger May Be Restarted After a Battery Conditioning Cycle Has Been Completed * Write Only. Read Will NACK * Writing a 0 to This Bit Will Be Ignored * Not Supported by LTC1759 * Not Supported by LTC1759 * Write Only. Read Will NACK * Intended for Host * Not Supported by LTC1759 * Write Only. Read Will NACK * Intended for Host * Not Supported by LTC1759 * Write Only. Read Will NACK * Intended for Host * Not Supported by LTC1759 * Write Only. Read Will NACK * Intended for Host * Not Supported by LTC1759 * Write Only. Read Will NACK * Intended for Host * Not Supported by LTC1759 * Write Only. Read Will NACK * Intended for Host * Not Supported by LTC1759 * Write Only. Read Will NACK * * * * Intended for Host All Bits Set High Prior to AlarmWarning() Transmission Not Supported by LTC1759 Write Only. Read Will NACK Reserved REMAINING_ CAPACITY_ALARM REMAINING_TIME_ ALARM INITIALIZED 10 9 - - 8 - 7 - DISCHARGING 6 - FULLY_CHARGED 5 - FULLY_DISHARGED 4 - ERROR 3:0 - LTC_VERSION 15:0 0101hex * Returns LTC Version Number * Read Only * Always Returns 0101hex
requirements with as much as 150pF on each SMBus signal. The improved rise time will benefit all of the devices which use the SMBus, especially those devices that use the I2C logic levels. Note that the dynamic pull-up circuits only pull to VDD, so some SMBus devices that are not compliant to the SMBus specifications may still have rise time compliance problems if the SMBus pull-up resistors are terminated with voltages higher than VDD.
15
LTC1759
OPERATIO
The Charger Controller Block The LTC1759 charger operations are handled by the charger controller block. This block is capable of charging the selected battery autonomously or under host control. The charger controller can request communications with the system management host (SMHost) by asserting INTB = 0; this will cause the SMHost, if present, to poll the LTC1759. The charger controller receives SMBus slave commands from the SMBus controller block. The charge controller allows the LTC1759 to meet the following Smart Battery-controlled (Level 2) charger requirements: 1. Implements the Smart Battery's critical warning messages over the SMBus. 2. Operates as an SMBus slave device that responds to ChargingVoltage() and ChargingCurrent() commands and adjusts the charger output characteristics accordingly.
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The charger controller allows the LTC1759 to meet the following host-controlled (Level 3) Smart Battery charger requirements. 1. In a host-controlled system the host is able to operate as an SMBus master device. 2. The host may determine the appropriate charging algorithm by querying the battery or providing an alternative special charging algorithm. 3. The host may control charging by disabling the Smart Battery's ability to transmit ChargingCurrent() and ChargingVoltage() request functions and broadcasting the charging commands to the LTC1759 over the SMBus. 4. The LTC1759 will still respond to Smart Battery critical warning messages without host intervention. The charger controller block uses the state machine of Figure 3. The functional features for state transitions and general control are detailed in Table 3.
15 0 7 1 OR 2 15 8 OR 9 15 CHARGING_CONTROLLED_STATE 21 CHARGING_RESET_STATE 19 14 CHARGING_WAKE-UP_STATE 20 3 OR 4 OR 5 OR 6 OR 16 15 8 OR 9 10 OR 11 OR 12 OR 13 OR 16 CHARGING_NONE_STATE 22
1759 F03
NOTE: NUMBERS REFER TO CONDITIONS AND STATE DESCRIPTION IN TABLE 3
Figure 3. Charger Controller State Machine
LTC1759
OPERATIO
# 0 CONDITION POWER_ON_RESET = 1
Table 3. Charger_Controller Functional Features
ACTION CHARGING_RESET_STATE =1 (Asynchronously Reset the Charger_Controller State Machine During Power-On Reset) CHARGING _WAKE-UP_STATE = 1 The Charger_Controller Will "Wake Up" Charge the Battery at IWAKE-UP Indefinitely CHARGING_WAKE-UP_STATE = 1 The Charger_Controller Will "Wake Up" Charge the Battery at IWAKE-UP Until Condition 3 Is Met CHARGING_NONE_STATE = 1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met CHARGING_NONE_STATE =1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met CHARGING_NONE_STATE = 1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met CHARGING_NONE_STATE = 1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met CHARGING_WAKE-UP_STATE =1 The Charger_Controller Stops Charging the Selected Battery. The Timer Continues to Run. The Charger Can Resume "Wake-Up" Charging If INHIBIT_CHARGE = 0 CHARGING_CONTROLLED_STATE = 1 The Charger_Controller Will Supply "Controlled Charge" to the Battery as Specified in the Current and Voltage Commands CHARGING_CONTROLLED_STATE = 1 The Charger_Controller Will Supply "Controlled Charge" to the Battery as Specified in the Current and Voltage Commands CHARGING_NONE_STATE = 1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met CHARGING_NONE_STATE = 1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met
1
CHARGING_RESET_STATE = 1 AND the Battery Is Present AND AC_PRESENT = 1 AND INHIBIT_CHARGE = 0 AND Thermistor Is Ideal CHARGING_RESET_STATE = 1 AND the Battery Is Present AND AC_PRESENT =1 AND INHIBIT_CHARGE = 0 AND THERM_ UR = 1 OR THERM_COLD = 1 CHARGING_WAKE-UP_STATE = 1 AND the Time-Out Period Exceeds tTIMEOUT AND THERM_UR = 1 OR THERM_COLD = 1
2
3
4
CHARGING_WAKE-UP_STATE = 1 AND an AlarmWarning() Message Is Received with Any Bit in the Upper Nibble Set
5
CHARGING_WAKE-UP_STATE = 1 (from Condition 1 above) AND THERM_HOT Changes from 0 to 1 AND THERM_UR = 0
6
CHARGING_WAKE-UP_STATE = 1 (from Condition 2 above) AND THERM_UR Changes from 1 to 0 AND THERM_HOT = 1
7
CHARGING_WAKE-UP-STATE = 1 AND INHIBIT_CHARGE Is Set to 1
8
(CHARGING_WAKE-UP_STATE = 1 OR CHARGING_NONE_STATE = 1) AND (Both ChargingCurrent() AND ChargingVoltage() Commands Are Received within tTIMEOUT) AND INHIBIT_CHARGE = 0 AND THERM_HOT = 0 (CHARGING_WAKE-UP_STATE = 1 OR CHARGING_NONE_STATE = 1) AND (Both ChargingCurrent() AND ChargingVoltage() Commands Are Received within tTIMEOUT) AND INHIBIT_CHARGE = 0 AND THERM_UR = 1 CHARGING_CONTROLLED_STATE = 1 AND No New ChargingCurrent() and ChargingVoltage() Commands Are Received for a Time-Out Period of tTIMEOUT CHARGING_CONTROLLED_STATE = 1 The Charger_Controller Is Supplying "Controlled Charge" to the Battery AND (an AlarmWarning() Message Is Received with Any Bit in the Upper Nibble Set)
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17
LTC1759
OPERATIO
# 12 CONDITION
CHARGING_CONTROLLED_STATE = 1 AND THERM_HOT Changes from 0 to 1 AND THERM_UR = 0
13
CHARGING_CONTROLLED_STATE = 1 AND THERM_UR Changes from 1 to 0 AND THERM_HOT = 1
14
CHARGING_CONTROLLED_STATE = 1 AND INHIBIT_CHARGE Is Set to 1
15
ANY STATE The Charger_Controller Is in Any State AND (the Battery Is Removed OR AC_PRESENT = 0 OR a 1 Is Written to POR_RESET) NOTE: Condition 15 Takes Precedence Over Any Other Condition. (CHARGING_CONTROLLED_STATE = 1) OR CHARGING_WAKE-UP_STATE = 1) AND A 1 Is Written to RESET_TO_ZERO
16
18
ANY STATE AND AC_PRESENT Transitions 0 to 1 or 1 to 0 OR BATTERY_PRESENT Transitions 0 to 1 or 1 to 0
19 20 21
CHARGING_RESET_STATE = 1 CHARGING _WAKE-UP_STATE = 1 CHARGING_CONTROLLED_STATE = 1
22
CHARGING_NONE_STATE = 1
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ACTION CHARGING_NONE_STATE = 1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met CHARGING_NONE_STATE = 1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met CHARGING_CONTROLLED_STATE = 1 INHIBIT_CHARGE Asynchronously Inhibits Charging Without Affecting the Charger_Controller State Machine. This Means the Charger Stops Charging the Battery but Continues to Accept New ChargingCurrent() and ChargingVoltage() Commands, Continues to Monitor the Battery Thermistor Input and Continues to Track the Communication Time-Out. It Will Resume Charging the Battery If INHIBIT_CHARGE Is Cleared to 0, Possibly at Different Current and Voltage If New Commands Have Been Sent in the Interim CHARGING_RESET_STATE= 1 The Charger_Controller Is Set to Its Power-On Default State CHARGING_NONE_STATE = 1 The Charger_Controller Stops Charging the Battery. It Cannot "Wake Up" Charge Again Until Condition 15 Is Met. It Can Supply "Controlled Charge" to the Battery If Conditions 8 or 9 Are Met. The Valid Charge Command Timer Is Cleared When RESET_TO_ZERO = 1. This Prevents Charging from Continuing Until After a Valid ChargeCurrent() and ChargeVoltage() Pair Is Received Alert SMHost of Change by Setting INTB = 0 CHGEN = 0 The Charger Is Not Charging CHGEN = ~INHIBIT_CHARGE The Charger Will Provide a Wake-Up Current When CHGEN = 1 CHGEN = ~INHIBIT_CHARGE The Charger Will Provide Specified Charging Voltage and Current When CHGEN = 1 A Zero Value for ChargingVoltage() Is Handled by Forcing CHGEN = 0 CHGEN = 0 The Charger Is Not Charging
LTC1759
OPERATIO
The Thermistor Decoder Block This block measures the resistance of the battery's thermistor and features high noise immunity at critical trip points. The low power standby mode supports all SMB charger reporting requirements when AC is not present. The thermistor decoder is shown in Figure 4. Thermistor sensing is accomplished by a state machine that reconfigures the switches of Figure 4 using RNR_SELB and RUR_SELB. The three allowable modes are as follows: 1. Overrange Detection. The RUR_SELB and RNR_SELB switches are off and the external RWEAK resistor forms a voltage divider with RTHERM. The resulting voltage is monitored at THERM, compared to an internal reference and sampled at the output of the OR comparator. This detection mode is always active allowing low power operation when AC power is not available. 2. Cold/Ideal/Hot Range Detection. The RNR_SELB switch is on and the RUR_SELB switch is off. The external RNR and RWEAK resistors form a voltage divider
RWEAK 475k 1% RNR 10k RUR 1% 1k 1%
HYSTERESIS
OR
Figure 4. Thermistor Decoder Block
-
+
-
+
TOTAL PARASITIC CAPACITANCE MUST BE LESS THAN 75pF
RTHERM
UR
-
+
-
+
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with RTHERM. The resulting voltage is monitored at THERM, compared to an internal reference and sampled at the output of the cold and hot comparators. This detection mode is only activated if OR tested low. 3. Underrange Detection. The RNR_SELB switch is off and the RUR_SELB switch is on. The external RUR and RWEAK resistors form a voltage divider with RTHERM. The resulting voltage is monitored at RNR, compared to an internal reference and sampled at the output of the UR comparators. This detection mode is only activated if HOT tested high. NOTE: The underrange detection scheme is a very important feature of the LTC1759. The RUR/RTHERM divider trip point of 0.333 * VDD (1V) is well above the 0.047 * VDD (140mV) threshold of a system using a 10k pull-up. A system using a 10k pull-up would not be able to resolve the important underrange to hot transition point with a modest 100mV of ground offset between battery and thermistor detection circuitry. Such offsets are anticipated when charging at normal current levels.
VDD RNR_SELB RNR VDD VDD VDD RUR_SELB THERM COLD THERM_COLD THERM LATCH HOT THERM_UR THERM_HOT THERM_OR
1759 F04
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LTC1759
OPERATIO
When AC power is not available the thermistor block supports the following low power operating features: 1. Only the low power THERM_OR detection circuitry is kept alive to support battery present interrupts. 2. The ChargeStatus() read function forces the thermistor block to update thermistor status at the beginning of the read. The low power mode is immediately reentered upon completion of the read. The thermistor impedance is interpreted according to Table 4.
Table 4. Thermistor State Ranges
THERMISTOR RESISTANCE 0 to 500 CHARGE STATUS BITS THERM_UR, THERM_HOT BATTERY_PRESENT THERM_HOT BATTERY_PRESENT (NONE) BATTERY_PRESENT THERM_COLD BATTERY_PRESENT THERM_OR THERM_COLD DESCRIPTION Underrange
500 to 3k 3k to 30k 30k to 100k Above 100k
Overrange
VLIMIT RLIMIT
25k
Table 5. Thermistor External Resistor Values
EXTERNAL RESISTOR RWEAK RUR RNR VALUE () 475k 1% 1k 1% 10k 1%
12.5k
Figure 5. Simplified VLIMIT Circuit Concept (ILIMIT Is Similar)
Note: The maximum allowed total external capacitance on THERM and RNR is 75pF, due to settling time requirements.
The VLIMIT Decoder Block The value of an external resistor connected from this pin to GND determines one of five voltage limits that are applied to the charger output value. These limits provide a measure of safety with a hardware restriction on charging voltage which cannot be overridden by software.
The ILIMIT Decoder Block The value of an external resistor connected from this pin to GND determines one of four current limits that are used to limit the maximum charging current value. These limits
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+
-
The required values for RWEAK, RUR and RNR are shown in Table 5.
25k
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25k +
+
-
33k
+
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provide a measure of safety with a hardware restriction on charging current which cannot be overridden by software.
Table 6. ILIMIT Trip Points and Ranges
EXTERNAL RESISTOR (RILIMIT) 0 10k 1% 33k 1% NOMINAL CHARGING CURRENT RANGE GRANULARITY 0 < I < 1023mA 0 < I < 2046mA 0 < I < 4092mA 0 < I < 8184mA 1mA 2mA 4mA 8mA ILIMIT VOLTAGE VILIMIT < 0.09VDD 0.17VVDD < VILIMIT < 0.34VVDD 0.42VVDD < VILIMIT < 0.59V Open (>250k, 0.66VVDD < VILIMIT or Short to VDD)
VDD
Hot
AC_PRESENT
Ideal Cold
12.5k
4 VLIM [3:0] ENCODER
1759 F05
LTC1759
OPERATIO
EXTERNAL RESISTOR (RVLIMIT) 0 10k 1% 33k 1%
Table 7. VLIMIT Trip Points and Ranges
NOMINAL CHARGING VOLTAGE (VOUT) RANGE 2465mV < VOUT < 8432mV 2465mV < VOUT < 12640mV 2465mV < VOUT < 16864mV 2465mV < VOUT < 21056mV 2465mV < VOUT < 32768mV
VLIMIT VOLTAGE VVLIMIT < 0.09VVCCP 0.17VVDD < VVLIMIT < 0.34VVDD 0.42VVCCP < VVLIMIT < 0.59VVDD
GRANULARITY 16mV 16mV 32mV
CHARGER VOUT (V)
100k 1% 0.66VVDD < VVLIMIT < 0.84VVDD Open or 0.91VVDD < VVLIMIT Tied to VDD
The Voltage DAC Block Note that the charge output voltage is offset by VREF. Therefore, the value of VREF is subtracted from the SMBus ChargingVoltage() value in order for the output voltage to be programmed properly (without offset). If the ChargingVoltage() value is below the nominal reference voltage of the charger, nominally 2.465V, the charger output voltage is programmed to zero. In addition, if the ChargingVoltage() value is above the limit set by the VLIMIT pin, then the charger output voltage is set to the value determined by the VLIMIT resistor and the VOLTAGE_OR bit is set. These limits are demonstrated in Figure 6. The Current DAC Block The current DAC is a delta-sigma modulator which controls the effective value of an external resistor, RSET, used to set the current limit of the charger. Figure 7 is a simplified diagram of the DAC operation. The delta-sigma modulator and switch convert the ChargingCurrent() value, received via the SMBus, to a variable resistance equal to: 1.25RSET/ChargingCurrent()/ILIMIT[x]) Therefore, programmed current is equal to: 0.8VREF/RSET (ChargingCurrent()/ILIMIT[x]), for ChargingCurrent() < ILIMIT[x]. When a value less than 1/16th of the maximum current allowed by ILIMIT is applied to the current DAC input, the current DAC enters a different mode of operation. The current DAC output is pulse width modulated with a high
RSET ISET
VREF
- MODULATOR
Figure 7. Current DAC Operation
ILIMIT/8 0 ~40ms
1750 F08
Figure 8. Charging Current Waveform in Low Current Mode
frequency clock having a duty cycle value of 1/8. Therefore, the maximum output current provided by the charger is IMAX/8. The delta-sigma output gates this low duty cycle signal on and off. The delta-sigma shift registers are then clocked at a slower rate, about 45ms/bit, so that the charger has time to settle to the IMAX/8 value. The resulting average charging current is equal to that requested by the ChargingCurrent() value.
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25 20 15 10 5 0 0 5
32mV 32mV
20 15 10 25 30 PROGRAMMED VALUE (V)
35
NOTE: THE USER MUST ADJUST THE VALUE OF THE EXTERNAL CURRENT SENSING COMPONENTS (RS1, RS2, RSENSE, RSET) TO MAINTAIN CONSISTENCY WITH ILIMIT RANGES. SEE APPLICATIONS INFORMATION
1759 F06
Figure 6. Transfer Function of Charger
IPROG (FROM CA1 AMP)
PROG TO ERROR AMP
CHARGINGCURRENT() VALUE
1759 F07
AVERAGE CHARGER CURRENT
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LTC1759
OPERATIO
When wake-up is asserted to the current DAC block, the delta-sigma is then fixed at a value equal to 80mA, independent of the ILIMIT setting. Note: The external resistor connected to the ISET pin must be multiplied by 0.8 to compensate for the 80% maximum duty cycle of the sigma-delta modulator. Note also that the 80% duty cycle converts the rise/fall time mismatches to a small gain error, rather than a nonlinearity. The parasitic
APPLICATIONS INFORMATION
Adapter Limiting An important feature of the LTC1759 is the ability to automatically adjust charging current to a level which avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being charged without complex load management algorithms. Additionally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. This feature is created by sensing total adapter output current and adjusting charging current downward if a preset adapter current limit is exceeded. True analog control is used, with closed loop feedback ensuring that adapter load current remains within limits. Amplifier CL1 in Figure 9 senses the voltage across RS4, connected between the CLP and CLN pins. When this voltage exceeds 92mV, the amplifier will override programmed charging current to limit adapter current to 92mV/RS4. A lowpass filter formed by 500 and 1F is required to eliminate switching noise. If the current limit is not used, both CLP and CLN pins should be connected to VCC. Setting Input Current Limit To set the input current limit, you need to know the minimum wall adapter current rating. Subtract 5% for the input current limit tolerance and use that current to determine the resistor value. RS4 = 92mV/ILIMIT ILIMIT = Adapter Min Current - (Adapter Min Current * 5%)
+
CL1 92mV
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capacitance at the ISET pin should be minimized to keep these errors small. The Battery Monitor Block (PWR_FAIL) Two internal resistor dividers compare the BAT2 terminal to the DCIN terminal. When BAT2 is above 89% of the voltage at DCIN the PWR_FAIL bit is set to 1. A small amount of proportional hysteresis, ~ 2%, is used for noise immunity. The PWR_FAIL bit is set low if AC_PRESENT is low.
+
CLP 1F
-
CLN
500 AC ADAPTER INPUT VIN
1759 F09
VCC LTC1759 92mV ADAPTER CURRENT LIMIT
RS4*
+
CIN
*RS4 =
Figure 9. Adapter Current Limiting
Table 7. Common RS4 Resistor Values
ADAPTER RATING (A) 1.5 1.8 2 2.3 2.5 2.7 3 RS4 VALUE* () 1% 0.06 0.05 0.045 0.039 0.036 0.033 0.03 RS4 POWER DISSIPATION (W) 0.135 0.162 0.18 0.206 0.225 0.241 0.27 RS4 POWER RATING (W) 0.25 0.25 0.25 0.25 0.5 0.5 0.5
* Values shown above are rounded to nearest standard value.
As is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see Table 7).
LTC1759
APPLICATIONS INFORMATION
Charge Termination Issues Batteries with constant current charging and voltagebased charger termination might experience problems with reductions of charger current caused by adapter limiting. It is recommended that input limiting feature be defeated in such cases. Consult the battery manufacturer for information on how your battery terminates charging. Setting Output Current Limit (Refer to Figure 10) The LTC1759 current DAC and the PWM analog circuitry must coordinate the setting of the charger current. Failure to do so will result in incorrect charge currents.
Table 8. Recommended Resistor Values
IMAX (A) 1.023 2.046 4.092 8.184 RSENSE () 1% 0.100 0.05 0.025 0.012 RSENSE (W) 0.25 0.25 0.5 1 RS1 = RS2 () 1% 200 200 200 200 RSET () 1% 3.83k 3.83k 3.83k 4.02k RILIMIT () 1% 0 10k 33k Open
Warning DO NOT CHANGE THE VALUE OF RILIMIT DURING OPERATION. The value must remain fixed and track the RSENSE
R1 15.8k Q1 AC ADAPTER INPUT C9, 0.1F
+
C15 10F 35V VDD Al
C14 0.1F
7 16 4 5 12
LTC1759 UV VDD SYNC SDB CHGEN VLIMIT ILIMIT DGND ISET PROG VC COMP1 AGND RNR THERM SDA SCL INTB DCIN DCDIV INFET VCC CLP CLN TGATE BOOSTC GBIAS BOOST SW BGATE SPIN SENSE BAT1 BAT2 VSET PGND
RVLIMIT, 33k RILIMIT, 33k RSET, 3.83k C11, 1F C13, 0.33F C12, 0.68F R4, 1.5k R7, 1k
25 24 18 17 28 27 11 6 20 19
VDD RWEAK 475k RNR 10k RUR 1k
14 15 13
D1: MBRS130LT3 D2: FMMD7000 L1: SUMIDA CDRH127-150
Q1: Si3457DV Q2, Q3: Si3456DV
Figure 10. 4A SMBus Smart Battery Charger
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and RSET values at all times. Changing the current setting can result in currents that greatly exceed the requested value and potentially damage the battery or overload the wall adapter if no input current limiting is provided. Example Calculations Setting up the output current to the desired value involves calculating these values: 1. RSENSE: This resistor is the current sense resistor on the charger output. 2. RSET: This resistor sets the current DAC output programming current scale. 3. RILIMIT: This resistor programs the full-scale value of the current DAC (IMAX). The value of RSENSE and RSET are directly related to each other based on the values chosen for RS1 and RS2. To prevent current sense op amp input bias errors, the value of RS1 and RS2 are kept the same, about 200. RSET is used to scale the PROG pin current relative to the RSENSE voltage drop to set the maximum current value. The following example is for a 4A design.
R2 1k RCL, 0.033
22 21 8 32 9 10 2 33 34 1 3 35 30 29 31 23 26 36 D2 D2 C5, 2.2F C2 0.47F
R3 499 C1 1F SYSTEM POWER C16 22F
C4, 0.1F C6 0.68F
Q2
L1 15H
RSENSE 0.025
+
Q3 D1
C3 22F
SMART BATTERY
RS1, 200 RS2, 200 R6 68 C8 0.047F C7 0.015F INTB SCL SDA
SMBus TO HOST
1759 F10
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LTC1759
APPLICATIONS INFORMATION
Step 1: Determine RSENSE. Using your chosen IMAX for your maximum charge current, calculate the sense resistor value and round to the nearest standard value. Any rounding error is made up by the RSET resistor calculation. The value of the VSENSE voltage is user-definable. A good trade-off between minimize power dissipation in the current sense resistor and maintaining good current scale accuracy is to use VSENSE = 100mV for full-scale current. RSENSE = VSENSE/IMAX RSENSE = 0.1V/4.092A = 0.024 Use RSENSE = 0.025 Step 2: Determine the value of RSET. VREF is 2.465V. Round RSET to the nearest standard value. RSET = VREF/(1.25 * IMAX) * RS1/RSENSE RSET = 2.465/(1.25 * 4.092) * 200/0.025 = 3.855k Use RSET = 3.83k Step 3: Determine the value of RILIMIT. This is simply a lookup function based on your IMAX value. See the Electrical Characteristics table for allowable RILIMIT values. Refer to Table 8 per recommended resistor values. Inductor Selection Higher operating frequencies allow the use of smaller inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition, the effect of inductor value on ripple current and low current operation must also be considered. The inductor ripple current IL decreases with higher frequency and increases with higher VIN. IL = V 1 VOUT 1 - OUT ( f)(L) VIN efficiency in the upper range of low current operation. In practice 15H is the lowest value recommended for use. Calculating IC Power Dissipation The power dissipation of the LTC1759 is dependent upon the gate charge of Q2 and Q3. The gate charge is determined from the manufacturer's data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the FET. PD = (VVCC - VGBIAS)[fPWM(QG2 + QG3)] + VVCC * IVCC Example: VVCC = 18V, VGBIAS = 9.1V, fPWM = 230kHz, QG2 = QG3 = 20nC, IVCC = 20mA. PD = (18V - 9.1V)(230kHz * 40nC) + 18V * 20mA = 441mW Soft Start and Undervoltage Lockout The LTC1759 is soft started by the 0.33F capacitor on the VC pin. On start-up, VC pin voltage will rise quickly to 0.5V, then ramp up at a rate set by the internal 45A pull-up current and the external capacitor. Battery charging current starts ramping up when VC voltage reaches 0.7V and full current is achieved with VC at 1.1V. With a 0.33F capacitor, time to reach full charge current is about 10ms and it is assumed that input voltage to the charger will reach full value in less than 10ms. The capacitor can be increased up to 1F if longer input start-up times are needed. In any switching regulator, conventional timer-based soft starting can be defeated if the input voltage rises much slower than the time out period. This happens because the switching regulators in the battery charger and the computer power supply are typically supplying a fixed amount of power to the load. If input voltage comes up slowly compared to the soft start time, the regulators will try to deliver full power to the load when the input voltage is still well below its final value. If the adapter is current limited, it cannot deliver full power at reduced output voltages and the possibility exists for a quasi "latch" state where the adapter output stays in a current limited state at reduced output voltage. For instance, if maximum charger plus computer load power is 30W, a 15V adapter might be current limited at 2.5A. If adapter voltage is less than (30W/2.5A = 12V) when full power is drawn, the adapter
Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IL = 0.4(IMAX). Remember the maximum IL occurs at the maximum input voltage. The inductor value also has an effect on low current operation. The transition to low current operation begins when the inductor current reaches zero while the bottom MOSFET is on. Lower inductor values (higher IL) will cause this to occur at higher load currents, which can cause a dip in
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LTC1759
APPLICATIONS INFORMATION
voltage will be pulled down by the constant 30W load until it reaches a lower stable state where the switching regulators can no longer supply full load. This situation can be prevented by utilizing the DCDIV resistor divider, set higher than the minimum adapter voltage where full power can be achieved. Input and Output Capacitors In the 4A Lithium Battery Charger (Figure 10), the input capacitor (C14) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. Worst-case RMS ripple current will be equal to one half of output charging current. Actual capacitance value is not critical. Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package, but caution must be used when tantalum capacitors are used for input or output bypass. High input surge currents can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when subjected to very high turn-on surge currents. Only Kemet T495 series of "Surge Robust" low ESR tantalums are rated for high surge conditions such as battery to ground. The relatively high ESR of an aluminum electrolytic for C15, located at the AC adapter input terminal, is helpful in reducing ringing during the hot-plug event. Highest possible voltage rating on the capacitor will minimize problems. Consult with the manufacturer before use. Alternatives include new high capacity ceramic (at least 20F) from Tokin, United Chemi-Con/Marcon, et al. However, using ceramic capacitors in the output filter of the charger can lead to acoustic noise radiation that can be confused with instability. At low charge currents, the charger operates in discontinuous current mode at an audible frequency. Other alternative capacitors include OSCON capacitors from Sanyo. The output capacitor (C3) is also assumed to absorb output switching current ripple. The general formula for capacitor current is: V 0.29 (VBAT) 1 - BAT VCC IRMS = (L1)(f)
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(
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For example, VCC = 19V, VBAT = 12.6V, L1 = 10H, and f = 200kHz, IRMS = 0.6A. EMI considerations usually make it desirable to minimize ripple current in the battery leads, and beads or inductors may be added to increase battery impedance at the 200kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and the battery impedance. If the ESR of C3 is 0.2 and the battery impedance is raised to 4 with a bead or inductor, only 5% of the current ripple will flow in the battery. Charger Crowbar Protection If VIN connector of Figure 1 charger can be instantaneously shorted (crowbarred) to ground, then a small P-channel FET M4 should be used to fast turn off the input P-channel FET M3 (see Figure 11), otherwise, high surge current might damage M3. M3 can also be replaced by a diode if dropout voltage and heat dissipation are not problems. Note that LT1759 will operate even when VBAT is grounded. If VBAT of Figure 1 charger gets shorted to ground very quickly (crowbarred) from a high battery voltage, slow loop response may allow charge current to build up and damage the topside N-channel FET M1. A small diode D5 (see Figure 12) from SDB pin to VBAT will shut down switching and protect the charger. Note that M4 and/or D5 are needed only if the charger system can be potentially crowbarred. Protecting SMBus Inputs The SMBus inputs, SCL and SDA, are exposed to uncontrolled transient signals whenever a battery is connected to the system. If the battery contains a static charge, the SMBus inputs are subjected to ESD which can cause damage after repeated exposure. Also, if the battery's positive terminal makes contact to the connector before the negative terminal, the SMBus inputs can be forced
25
LTC1759
APPLICATIONS INFORMATION
below ground with the full battery potential, causing a potential for latch-up in any of the devices connected to the SMBus inputs. Therefore it is good design practice to protect the SMBus inputs as shown in Figure 13. PCB Layout Considerations The LTC1759 has two layout critical areas. The first is the ISET pin and the second is the DC/DC converter switching circuity. ISET Pin Layout: The LTC1759 ISET pin lead length is critical and should be kept to a minimum to reduce parasitic capacitance. Any parasitic capacitance on this node will cause errors in the programmed current values. Place RSET resistor directly next to the ISET pad. The trace from RSET to the LTC1759 PROG pin pad is not critical. DC/DC PCB Layout Hints: For maximum efficiency, the switch node rise and fall time is kept as short as possible. To prevent magnetic and electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC is essential, especially the power paths (primary and secondary). 1. Keep the highest frequency loop path as small and tight as possible. This includes the bypass capacitors, with the higher frequency capacitors being closer to the noise source than the lower frequency capacitors. The
M3 VIN M4 TPO610 LTC1759 INFET RS4 VCC
1759 F11
Figure 11. VIN Crowbar Protection
CHGEN 100k SDB D5 1N4148
1759 F12
LTC1759
VBAT
Figure 12. VBAT Crowbar Protection
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highest frequency power path loop has the highest layout priority. For best results, avoid using vias in this loop and keep the entire high frequency loop on a single external PCB layer. If you must, use multiple vias to keep the impedance down (see Figure 15). 2. Run long power traces in parallel. Best results are achieved if you run each trace on separate PCB layer one on top of the other for maximum capacitance coupling and common mode noise rejection. 3. If possible, use a ground plane under the switcher circuitry to minimize capacitive interplane noise coupling. 4. Keep signal or analog ground separate. Tie this analog ground back to the power supply at the output ground using a single point connection. 5. For best current programming accuracy provide a Kelvin connection from RSENSE to RS1 and RS2. See Figure 14 as an example. Interfacing with a Selector The LTC1759 is designed to be used with a true analog multiplexer for the thermistor sensing path. Some selector ICs from various manufacturers may not implement this. Consult LTC applications department for more information. Electronic Loads The LTC1759 is designed to work with a real battery. Electronic loads will create instability within the LTC1759 preventing accurate programming currents and voltages. Consult LTC applications department for more information.
VDD FOR ESD PROTECTION CONNECTOR TO BATTERY TO SYSTEM FOR ESD AND LATCH-UP PROTECTION
1759 F13
Figure 13
LTC1759
APPLICATIONS INFORMATION
Charging Indication When a CHARGECURRENT() command with a value of zero is sent to the LTC1759, current stops flowing into the battery. However, the command does not cause the CHGEN pin to pull low. This prevents use of the CHGEN pin as a charge termination indication. Figure 16 shows a circuit that reliably indicates when the battery is receiving a charge current. The circuit shown, except for the optional 555 timer IC, filters out the ISET DAC 80kHz output into a smooth signal. Q1 and R5 partially isolate the capacitance of C1 from effecting the ISET pin of the LTC1759. Q1 is configured as a crude voltage level detector looking for voltage going below approximately one volt on the emitter. The RC circuit consisting of R4 and C1 filters low pulses from the ISET pin. Q2 buffers the RC filter circuit allowing a more logic level type interface. The circuit is powered from the logic output driver of the CHGEN pin of the LTC1759. The circuit does not need any capacitive supply bypassing to function and draws little current. When the CHGEN pin goes low, the current consumption of the circuit is eliminated. Note that some resistor values must change depending on the supply voltage connected to the VDD pin of the LTC1759. An optional low power 555 timer can be added to to give a blinking LED charge indication.
SWITCH NODE
DIRECTION OF CHARGING CURRENT
RSENSE
1759 F14
TO RS1 AND RS2
Figure 14. Kelvin Sensing of Charging Current
VDD 1 CHARGE R1 R1 3.3V = 240 5V = 510 2 3 4 LMC555 GROUND TRIGGER OUTPUT RESET VCC DISCHARGE THRESHOLD CONTROL VOLTAGE 8 7 6 5
CHARGE (H)
R4 4.7M G R6 R6 3.3V = 330k 5V = 680k R5 10k Q1 MMBT3904 R7 330k D Q2, 2N7002 S
C1 0.1F
Figure 16. Battery Charge Indicator Circuit
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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L1 VBAT HIGH FREQUENCY CIRCULATING PATH
VIN
CIN
D1
COUT
BAT
1759 F15
Figure 15. High Speed Switching Path
R2 4.7k C2 0.1F U2 LTC1759 UV VDD SYNC SDB CHGEN VLIMIT ILIMIT DGND ISET PROG VC COMP1 AGND RNR THERM SDA SCL INTB DCIN DCDIV INFET VCC BOOSTC CLP CLN TGATE SW BGATE BOOST GBIAS SPIN SENSE BAT1 BAT2 VSET PGND
1759 F16
R3 2.7M
(OPTIONAL, SEE TEXT)
C3 0.1F VDD
7 16 4 5 12 25 24 18 17 28 27 11 6 20 19 14 15 13
22 21 8 32 33 9 10 2 3 35 1 34 30 29 31 23 26 36
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LTC1759
TYPICAL APPLICATION
4A SMBus Smart Battery Charger
R1 15.8k Q1 AC ADAPTER INPUT C9, 0.1F R2 1k RCL, 0.033
+
C15 10F 35V VDD Al
C14 0.1F
RVLIMIT, 33k RILIMIT, 33k RSET, 3.83k C11, 1F C13, 0.33F C12, 0.68F R4, 1.5k R7, 1k
VDD RWEAK 475k RNR 10k RUR 1k
D1: MBRS130LT3 D2: FMMD7000 L1: SUMIDA CDRH127-150
PACKAGE DESCRIPTION
5.20 - 5.38** (0.205 - 0.212)
0 - 8 7.65 - 7.90 (0.301 - 0.311) 0.05 - 0.21 (0.002 - 0.008)
0.13 - 0.22 (0.005 - 0.009)
0.55 - 0.95 (0.022 - 0.037)
0.25 - 0.38 NOTE: DIMENSIONS ARE IN MILLIMETERS (0.010 - 0.015) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
0.65 (0.0256) BSC
RELATED PARTS
PART NUMBER LTC1473 LTC1479 LT1505 LT1511 LTC1694 LT1769 DESCRIPTION Dual PowerPath Switch Driver PowerPath Controller for Dual Battery Systems High Efficiency Constant-Current/Constant-Voltage Charger Monolithic 3A Constant-Current/Constant-Voltage Charger SMBus Accelerator in SOT-23 Package Monolithic 2A Constant-Current/Constant-Voltage Charger
TM
PowerPath is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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LTC1759 UV VDD SYNC SDB CHGEN VLIMIT ILIMIT DGND ISET PROG VC COMP1 AGND RNR THERM SDA SCL INTB DCIN DCDIV INFET VCC CLP CLN TGATE BOOSTC GBIAS BOOST SW BGATE SPIN SENSE BAT1 BAT2 VSET PGND
22 21 8 32 9 10 2 33 34 1 3 35 30 29 31 23 26 36 D2 D2 C5, 2.2F C2 0.47F
R3 499 C1 1F SYSTEM POWER C16 22F
C4, 0.1F C6 0.68F
Q2
L1 15H
RSENSE 0.025
+
Q3 D1
C3 22F
SMART BATTERY
RS1, 200 RS2, 200 R6 68 C8 0.047F C7 0.015F INTB SCL SDA
SMBus TO HOST
1759 F10
Q1: Si3457DV Q2, Q3: Si3456DV
Dimensions in inches (millimeters) unless otherwise noted. G Package 36-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
1.73 - 1.99 (0.068 - 0.078) 12.67 - 12.93* (0.499 - 0.509) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
G36 SSOP 1098
COMMENTS Switches Between Two Voltages Switches Two Batteries, AC Adapter and Charger Up to 97% Efficiency with Input Current Limiting Input Current Limiting; No External MOSFETs Improves SMBus Data Integrity Similar to LT1511 but 2A Rating, 28-Pin SSOP Package
1759fs, sn1759 LT/TP 0500 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

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